1. Field of the Invention
The present invention relates to a substrate for a display panel, a display panel having the substrate, a production process of the substrate and a production process of the display panel, and specifically relates to a substrate for a display panel such as a substrate for a liquid crystal panel having a layered structure which includes conductive films, semiconductive films and insulating films with given patterns, a display panel having the substrate, a production process of the substrate and a production process of the display panel.
2. Description of the Related Art
Some liquid crystal display panels include a TFT array substrate and a color filter which are disposed opposed to each other leaving a tiny space therebetween, and the space is filled with a liquid crystal.
On one surface of the TFT array substrate, thin films including conductive films, semiconductive films and insulating films with given patterns are stacked in a given order. These conductive films, semiconductive films and insulating films form TFTs (Thin Film Transistors) which are used for placing voltages to pixel electrodes. In addition, scanning signal lines (gate signal lines) which transmit scanning signals to gate electrodes of the TFTs, data signal lines (source signal lines) which transmit data signals to source electrodes of the TFTs, and other elements are made from the conductive films, and those elements are insulated from each other by the insulating films.
In addition to these elements, input pads for inspection (input terminals for inspection) with which an inspection probe is to be brought into contact at the time of lighting inspection of the liquid crystal display panel, and inspection line bundles which are to be used for connecting the input pads and the data signal lines or the source signal lines are sometimes provided on the TFT array substrate. The inspection line bundles are various in their structures, and one example thereof is a line bundle which straddles two conductive films between which an insulating film is sandwiched. To be specific, lines which make up the line bundle include sections made from one of the two conductive films between which the insulating film is sandwiched and sections made from the other conductive film. Contact holes are formed at given positions through the insulating film sandwiched therebetween, and the sections are electrically connected by the contact holes.
In the TFT array substrate having the above-described configuration, when the insulating film between the conductive films is broken and the conductive films are electrically connected at a position different from a designed position in a different manner, the TFTs, the data signal lines, the gate signal lines and other elements do not function sometimes as designed, which could cause display defects in the display panel. In addition, when the insulating film is broken in the inspection line bundles, the lighting inspection of the display panel cannot be performed successfully. As a result thereof, the presence of display defects in the display panel and their appearance cannot be detected accurately, and a problem therefore arises in quality control.
Causes of the break in the insulating film include electrical discharge resulting from a potential difference between the conductive films between which the insulating film is sandwiched. For example, in a production process of the substrate for a display panel, static electricity is built up in the conductive films in processes including sputtering and chemical vapor deposition (CVD) for depositing the conductive films and the insulating film, and in a sputtering process for patterning the deposited films. Also in other various processes, static electricity is built up in the conductive films. For example, peeling electrification occurs when the substrate is peeled from supporting tables (supporting stages) of various devices, and static electrification occurs from migration of static electricity which is built up in a human body when a worker touches the conductive films. After static electricity is built up in the conductive films, when the potential difference between the conductive films between which the insulating film is sandwiched goes beyond a withstand voltage of the insulating film, electrical discharge is made between the conductive films, and therefore insulation breakdown of the insulating film occurs.
In order to prevent the insulating film from being broken, the two conductive films between which the insulating film is sandwiched can be arranged to be short-circuited in a production process of a display panel (see Japanese Patent Application Unexamined Publication No. Hei05-303110). In Japanese Patent Application Unexamined Publication No. Hei05-303110, a configuration of a display panel is described in which an insulating film (a gate insulating film in this example) is formed on a transparent substrate on which scanning signal lines and gate electrodes of TFTs are formed such that one end of the formed scanning signal lines is exposed, and a conductive film which forms data signal lines, and source electrodes and drain electrodes of the TFTs is further formed on a surface of the insulating film. Then, in patterning the conductive film, a section which is in direct contact with a thin film pattern such as the scanning signal lines is left as it is. At a final stage of the production process of the TFT array substrate or the production process of the liquid crystal display panel using the TFT array substrate, the section is separated off.
By the configuration as described above, the conductive film which forms the data signal lines and other elements are electrically connected with the scanning signal lines and other elements at a stage of forming the conductive film, and the electrical connection is maintained until the electrically connected section is cut off. Thus, no potential difference arises between the scanning signal lines and other elements and the data signal lines and other elements, whereby insulation breakdown is prevented.
However, in the TFT array substrate having the above-described configuration, it is necessary that portions where source bus lines and gate bus lines are interconnected are placed on the substrate, so that design limitation is imposed on the substrate. In addition, it is necessary that gate metals are exposed in advance before patterning of the source bus lines.